1. Field of the Invention
The present invention relates to a sample hold circuit and an eliminating method thereof. More particularly, the present invention relates to a sample hold circuit and a method thereof for eliminating an offset voltage of an analog signal.
2. Description of Related Art
Most of physical signals generated in daily life are analog signals. However, since a digital signal is easy to be edited, analyzed, stored and has a better anti-noise capability, in an actual application, the analog signal is generally converted into the digital signal through an analog-to-digital converter (ADC).
The ADC plays an important role in wireless communication systems and portable video image devices, and as the wireless communication systems and the portable video image devices are quickly developed, demand for a high conversion speed of the ADC is increased. In various types of ADC structures, a pipelined ADC can achieve features of high-speed input and fast processing.
In a general ADC, a sample hold circuit is generally disposed at a front end thereof, which is used for holding the analog signal. Since a sampling time is very short, a sampling output is a series of discontinuous narrow pulses, so that certain time is required to digitalize each of the sampled narrow pulse signals. Therefore, between two samplings, the sampled analog signal is temporarily stored until a next sampling pulse is received, and such operation is referred to as “hold”. According to a basic principle of digital signal processing (i.e. the Nyquist sampling theorem), if the extracted analog signal is required to be accurately and truly rendered, a sampling frequency has to be higher than twice of a maximum frequency. Therefore, the conversion speed of the ADC is usually determined by an operation frequency of the sample hold circuit. As a signal processing speed of the ADC becomes higher, demand for the operation frequency of the corresponding sample hold circuit is accordingly increased. Therefore, to improve the operation frequency of the sample hold circuit to cope with an actual demand is an important subject.
FIG. 1 is an equivalent circuit diagram illustrating a conventional sample hold circuit in a hold state. FIG. 2 is a schematic diagram illustrating a plurality of capacitors C1A of FIG. 1 coupled to different voltages. Referring to FIG. 1 and FIG. 2, the conventional sample hold circuit 100 includes capacitors C3A, C4A, a plurality of capacitors C1A, a plurality of capacitors C2A, an operation amplifier 102 and a voltage generator 104. The voltage generator 104 is used for outputting reference voltages VRP and VRN. The embodiment of FIG. 2 has 8 capacitors C1A with different capacitances. The capacitances of the capacitors C1A are respectively C, C/2, C/4, C/8, C/16, C/32, C/64, and C/128. When the sample hold circuit 100 is in the hold state, the capacitors C1A and C2A are connected to the reference voltage VRP and/or the reference voltage VRN, so that the sample hold circuit 100 can eliminate a positive or a negative offset voltage of the sampled analog signal. Wherein, the reference voltage VRP is equal to a negative reference voltage VRN, i.e. VRP=−VRN. Moreover, a coupling approach of the capacitors C2A is the same to that of the capacitors C1A, so that detail description thereof is not repeated. Though the conventional sample hold circuit 100 can eliminate the positive or negative offset voltage of the sampled analog signal, in an actual application, a magnitude of the offset voltage can be different due to different environmental factors or a noise of the analog signal. The conventional sample hold circuit still uses the fixed number of the capacitors to eliminate the offset voltage even when the magnitude of the offset voltage of the analog signal is relatively small, and each of the capacitors is either coupled to the reference voltage or coupled to the reference voltage VRN, so that a large current is extracted from the voltage generator 104, and therefore the reference voltages are pulled down for a large potential. Therefore, a relatively longer time is taken for the reference voltage recovering back to its original potential, so that the operation speed of the sample hold circuit is limited, and accordingly a conversion efficiency of the ADC is reduced.